DESIGNANDANALYSISOFPHASELOCKEDLOOP

Abstract

 This study employs the 45nm CMOS technology (GPDK045library) in the CADENCE Vertuoso Analog
 Design Environment to develop a PLL system. The proposed PLL architecture comprises the following
 modules: a voltage controlled oscillator to produce the clock output, which is the multiplication of the input
 reference frequency and multiplication factor (N); a phase and frequency detector (PFD) to compare the phase
 (or frequency) of the input reference and the phase (or frequency) of the feedback signal and generate the
 difference or an error signal; a charge pump and loop filter to convert the digital UP and DOWN signals into
 analog control voltage; and a frequency divider to equalize the output frequency with the input frequency. With
 a lock time of 40µs, all modules are combined to generate a 1GHz output frequency from a 4MHz input
 frequency using a 1.8V DC supply. The output clock has a 44.87 ps period jitter